Energy Efficient UART Design Using Virtex-4, Virtex-5 and Virtex-6 FPGA

Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices

Problem statement: The development cost for Application Specific Integrated Circuits (ASICs) are high, algorithms should be verified and optimized before implementation. The Digital Signal Processing (DSP), image processing and multimedia requires extensive use of multiplication. The truncated multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. Approach: Th...

Virtex - 5 FPGA System Power Design Considerations

www.xilinx.com 1 © 2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. With the ever increasing power consumption trend in today's high-performance systems, managing the power within the system design budget is becoming as important as meeting ...

Introducing the New Virtex - 4 FPGA Family

Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs

A design for the detection and correction of single event upsets (SEUs) in the configuration memory of field programmable gate arrays (FPGAs) is presented. Larger configuration memories and shrinking design rules have caused concerns to rise about SEUs in highreliability high-availability systems using FPGAs. We describe the operation and architecture of the proposed design as well as its imple...

Reconfigurable Self - Organizing NN Design Using Virtex FPGA

In this paper, a self-organizing neural network model with entropy-based evaluator called EBE is proposed. An FPGA based design that implements the EBE model is presented. The PCI bus interface including DMA transfer is embedded into the design. 8-bit test data is fed into the design to verify the correctness of the algorithm and its FPGA implementation. Topic Area No.5 : Algorithms and Optimiz...